The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs). Typical transistor devices include gate electrodes as control electrodes that are formed overlying a semiconductor substrate, and spaced-apart source and drain regions that are formed within the semiconductor substrate and between which currents can flow. For a transistor device, a control voltage may be applied to the gate electrode and control the flow of current through a channel in the semiconductor substrate between the source and drain regions and beneath the gate electrode.
A transistor device is accessed via conductive contacts typically formed on the source/drain regions. Each conductive contact is usually formed by siliciding a metal on the source/drain regions and then depositing a dielectric layer over the silicided source/drain regions and etching a contact opening in the dielectric layer. Metal is then deposited in the contact opening to form the contact structure. At reduced technology nodes, more and more circuitry is incorporated on a single integrated circuit chip and the sizes of each individual device in the circuit and the spacing between device elements decreases. However, one of the limiting factors in the continued shrinking of integrated semiconductor devices is the resistance of contacts to doped regions such as the source and drain regions. As device sizes decrease, the width of contacts decreases. As the width of the contacts decreases, the resistance of the contacts becomes increasingly larger. In turn, as the resistance of the contacts increases, the drive current of the devices decreases, thus adversely affecting device performance. Therefore, the importance of reducing contact resistance at source/drain regions is amplified at reduced technology nodes.
Metal-insulator-semiconductor (MIS) contact structures may provide reduced contact resistance. MIS contact structures include a thin dielectric insulator layer that is positioned between semiconductor material, such as the semiconductor material of a source/drain region, and metal contact material. MIS contact structure may reduce the barrier height between the semiconductor and the metal contact structures, leading to lower contact resistance despite the additional resistance presented by the thin dielectric insulator layer.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits having metal-insulator-semiconductor contacts. In addition, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that utilize common metal layers to form contact interfaces with source/drain regions in both PFET areas and NFET areas. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.